EP9312 Datasheet, PDF (27/62 Pages) Cirrus Logic – Universal Platform System-on-chip Processor

Static Memory Single Read Wait Cycle
Parameter
CSn assert to WAIT time
WAIT assert time
WAIT to CSn deassert delay time
Symbol
t_WAITd
t_WAITpw
t_CSnd
Min
-
t_HCLK × 2
t_HCLK × 3
EP9312
Universal Platform SOC Processor
Typ
Max
Unit
-
t_HCLK × (WST1-2)
ns
-
t_HCLK × 510
ns
-
t_HCLK × 5
ns
AD
CSn
WRn
RDn
DQMn
DA
WAIT
t_WAITd
t_WAITpw
t_CSnd
Figure 14. Static Memory Single Read Wait Cycle Timing Measurement
DS515PP7
©Copyright 2005 Cirrus Logic (All Rights Reserved)
27