EP9312 Datasheet, PDF (25/62 Pages) Cirrus Logic – Universal Platform System-on-chip Processor

EP9312
Universal Platform SOC Processor
Static Memory Burst Read Cycle
Parameter
CSn assert to Address 1 transition time
Address assert time
AD transition to CSn deassert time
AD hold from CSn deassert time
CSn to RDn delay time
CSn to DQMn assert delay time
DA setup to AD transition time
DA setup to CSn deassert time
DA hold from AD transition time
DA hold from RDn deassert time
Symbol
t_ADd1
t_ADd2
t_ADd3
t_ADh
t_RDd
t_DQMd
t_DAs1
t_DAs2
t_DAh1
t_DAh2
Min
-
-
-
t_HCLK
-
-
15
t_HCLK + 12
0
0
Typ
t_HCLK × (WST1 + 1)
t_HCLK × (WST2 + 1)
t_HCLK × (WST1 + 2)
-
-
-
-
-
-
-
Max
-
-
-
-
3
1
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
t_ADs
AD
CSn
WRn
t_RDd
RDn
DQMn
t_DQMd
DA
WAIT
t_ADd1
t_ADd2
t_ADd2
t_ADd3
t_ADh
t_DAs1
t_DAh1
t_DAs1
t_DAh1
t_DAs1
t_DAh1
t_DAh2
t_DAs2
Figure 12. Static Memory Burst Read Cycle Timing Measurement
DS515PP7
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