CS4265_07 Datasheet, PDF (52/56 Pages) Cirrus Logic – 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
11.CHANNEL STATUS BUFFER MANAGEMENT
The CS4265 has a comprehensive channel status (C) data buffering scheme which allows the user to manage the
C data through the control port.
11.1 IEC60958-3 Channel Status (C) Bit Management
The CS4265 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384
bits). The user may read from, or write to, these RAM buffers through the control port.
The CS4265 manages the flow of channel status data at the block level, meaning that entire blocks of chan-
nel status information are buffered at the input, synchronized to the output time base, and then transmitted.
The buffering scheme involves a cascade of two block-sized buffers, named E and F, as shown in Figure 44.
The MSB of each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0
(which is at control port address 13h) is the consumer/professional bit for channel status block A.
The E buffer is accessible from the control port, allowing read and writing of the C data. The F buffer is used
as the source of C data for the IEC60958-3 transmitter. The F buffer accepts block transfers from the E buff-
er.
A
B
8-bits 8-bits
E
24
words
F
Transm it
D a ta
B u ffe r
To
AES3
Transm itter
Control Port
Figure 44. Channel Status Data Buffer Structure
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