CS4265_07 Datasheet, PDF (24/56 Pages) Cirrus Logic – 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

4. APPLICATIONS
CS4265
4.1 Recommended Power-Up Sequence
1. Hold RESET low until the power supply,MCLK, and LRCK are stable. In this state, the Control Port is
reset to its default settings.
2. Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The con-
trol port will be accessible.
3. The desired register settings can be loaded while the PDN bit remains set.
4. Clear the PDN bit to initiate the power-up sequence.
4.2 System Clocking
The CS4265 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three
speed modes as shown in Table 1.
Mode
Single-Speed
Double-Speed
Quad-Speed
Sampling Frequency
4-50 kHz
50-100 kHz
100-200 kHz
Table 1. Speed Modes
4.2.1 Master Clock
MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the
frequency at which audio samples for each channel are clocked into or out of the device. The FM bits (See
“Functional Mode (Bits 7:6)” on page 37.) and the MCLK Freq bits (See “MCLK Frequency - Address 05h”
on page 38.) configure the device to generate the proper clocks in Master Mode and receive the proper
clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and
LRCK frequencies.
LRCK
(kHz)
32
44.1
48
64
88.2
96
128
176.4
192
Mode
64x
-
-
-
-
-
-
8.1920
11.2896
12.2880
96x
-
-
-
-
-
-
12.2880
16.9344
18.4320
128x
-
-
-
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
QSM
MCLK (MHz)
192x
256x
384x
512x
-
8.1920 12.2880 16.3840
-
11.2896 16.9344 22.5792
-
12.2880 18.4320 24.5760
12.2880 16.3840 24.5760 32.7680
16.9344 22.5792 33.8680 45.1584
18.4320 24.5760 36.8640 49.1520
24.5760 32.7680
-
-
33.8680 45.1584
-
-
36.8640 49.1520
-
-
DSM
768x
1024x
24.5760 32.7680
33.8680 45.1584
36.8640 49.1520
-
-
-
-
-
-
-
-
-
-
-
-
SSM
Table 2. Common Clock Frequencies
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