CS4265_07 Datasheet, PDF (42/56 Pages) Cirrus Logic – 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See Table 16.
DACSoft
0
0
1
1
DACZeroCross
0
1
0
1
Mode
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled (default)
Table 16. DAC Soft Cross or Zero Cross Mode Selection
6.12.2 Invert DAC Output (Bit 5)
Function:
When this bit is set, the output of the DAC is inverted.
6.13 Status - Address 0Dh
7
Reserved
6
Reserved
5
Reserved
4
EFTC
3
ClkErr
2
Reserved
1
ADCOvfl
0
ADCUndrfl
For all bits in this register, a ‘1’ means the associated condition has occurred at least once since the register
was last read. A ‘0’ means the associated condition has NOT occurred since the last reading of the register.
Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register
defaults to 00h.
6.13.1 E to F C-Buffer Transfer
Function:
Indicates the completion of an E to F C-buffer transfer. See “Channel Status Buffer Management” on
page 52 for more information.
6.13.2 Clock Error (Bit 3)
Function:
Indicates the occurrence of a clock error condition.
6.13.3 ADC Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
6.13.4 ADC Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
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