CS4265_07 Datasheet, PDF (25/56 Pages) Cirrus Logic – 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

4.2.2
CS4265
Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 10.
MCLK Freq Bits
MCLK
÷1
000
÷1.5
001
÷2
010
÷3
011
÷4
100
÷256
00
÷128
01
÷64
10
FM Bits
÷4
00
÷2
01
÷1
10
LRCK
SCLK
Figure 10. Master Mode Clocking
4.2.3
Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sam-
ple rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x, 48x or 32x Fs, depending on the desired speed mode. Refer to Table 3 for required clock ra-
tios.
SCLK/LRCK Ratio
Single-Speed
32x, 48x, 64x, 128x
Double-Speed
32x, 48x, 64x
Quad-Speed
32x, 48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
4.3 High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4265, a small DC offset may be driven
into the A/D converter. The CS4265 includes a high-pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-
tichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPFFreeze bit (See “ADC High-Pass Filter Freeze (Bit 1)” on page 38.) is set during normal op-
eration, the current value of the DC offset for the each channel is frozen and this DC offset will continue to
be subtracted from the conversion result. This feature makes it possible to perform a system DC offset cal-
ibration by:
1. Running the CS4265 with the high-pass filter enabled until the filter settles. See the ADC Digital Filter
Characteristics section for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS4265.
DS657F2
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