CS4265_07 Datasheet, PDF (30/56 Pages) Cirrus Logic – 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
under the control of a register bit. The CS4265 also allows immediate muting of the IEC60958-3 transmit-
ter audio data through a control register bit.
External components are used to terminate and isolate the external cable from the CS4265. These com-
ponents are detailed in the “External IEC60958-3 Transmitter Components” section on page 51.
4.12.2 Mono Mode Operation
An IEC60958-3 stream may be used in more than one way to transmit 192 kHz sample rate data. One
method is to double the frame rate of the current format. This results is a stereo signal with a sample rate
of 192 kHz. An alternate method is implemented using the two sub-frames in a 96 kHz frame rate
IEC60958-3 signal to carry consecutive samples of a mono signal, resulting in a 192 kHz sample rate
stream. This allows older equipment, whose IEC60958-3 transmitters and receivers are not rated for
192 kHz frame rate operation, to handle 192 kHz sample rate information. In this “mono mode”, two ca-
bles are needed for stereo data transfer. The CS4265 offers Mono Mode operation. The CS4265 is placed
into and out of Mono Mode with the MMT control bit.
In Mono Mode, the input port will run at the audio sample rate (Fs), while the IEC60958-3 transmitter
frame rate will be at Fs/2. Consecutive left or right channel serial audio data samples may be selected for
transmission on the A and B sub-frames, and the channel status block transmitted is also selectable.
Using Mono Mode is only necessary if the incoming audio sample rate is already at 192 kHz and contains
both left and right audio data words. The “Mono Mode” IEC60958-3 output stream may also be achieved
by keeping the CS4265 in normal stereo mode and placing consecutive audio samples in the left and right
positions in an incoming 96 kHz word-rate data stream.
4.13 I²C Control Port Description and Timing
The control port is used to access the registers, allowing the CS4265 to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. A 47 kΩ pull-up
or pull-down on the SDOUT pin will set AD0, the least significant bit of the chip address. A pull-up to VLS
will set AD0 to ‘1’ and a pull-down to DGND will set AD0 to ‘0’. The state of the SDOUT pin is sensed and
AD0 is set upon the release of RESET.
The signal timings for a read and write cycle are shown in Figure 15 and Figure 16. A Start condition is de-
fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the
clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4265 after
a Start condition consists of a 7-bit chip address field and an R/W bit (high for a read, low for a write). The
upper 6 bits of the 7-bit address field are fixed at 100111. To communicate with a CS4265, the chip address
field, which is the first byte sent to the CS4265, should match 100111 followed by the setting of AD0. The
eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Point-
er (MAP), which selects the register to be read or written. If the operation is a read, the contents of the reg-
ister pointed to by the MAP will be output. Following each data byte, the memory address pointer will
automatically increment to facilitate block reads and writes of successive registers. Each byte is separated
by an acknowledge bit. The ACK bit is output from the CS4265 after each input byte is read, and is input to
the CS4265 from the microcontroller after each transmitted byte.
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