CS4265_07 Datasheet, PDF (39/56 Pages) Cirrus Logic – 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

6.6 Signal Selection - Address 06h
7
SDINSel
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
LOOP
6.6.1 DAC SDIN Source (Bit 7)
Function:
This bit is used to select the serial audio data source for the DAC as shown in Table 11.
SDINSel Setting
0
1
DAC Data Source
SDIN1
SDIN2
Table 11. DAC SDIN Source Selection
CS4265
0
Reserved
6.6.2
Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to
“Internal Digital Loopback” on page 28.
6.7 Channel B PGA Control - Address 07h
7
Reserved
6
Reserved
5
Gain5
4
Gain4
3
Gain3
6.7.1 Channel B PGA Gain (Bits 5:0)
Function:
See “Channel A PGA Gain (Bits 5:0)” on page 39.
2
Gain2
1
Gain1
0
Gain0
6.8 Channel A PGA Control - Address 08h
7
Reserved
6
Reserved
5
Gain5
4
Gain4
3
Gain3
2
Gain2
1
Gain1
0
Gain0
6.8.1 Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See Table 12 for ex-
ample settings.
Gain[5:0]
101000
000000
011000
Setting
-12 dB
0 dB
+12 dB
Table 12. Example Gain and Attenuation Settings
DS657F2
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