CS4265_07 Datasheet, PDF (31/56 Pages) Cirrus Logic – 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

CS4265
SCL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
SDA
1 0 0 1 1 1 AD0 0
76 54 3 210
76
ACK
ACK
10
76
ACK
10
START
Figure 15. Control Port Timing, I²C Write
DATA +n
76 10
ACK
STOP
SCL
SDA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CHIP ADDRESS (WRITE)
MAP BYTE
STOP
CHIP ADDRESS (READ)
DATA
DATA +1 DATA + n
1 0 0 1 1 1 AD0 0
7 6 5 4 3 210
1 0 0 1 1 1 AD0 1
70
70 70
START
ACK
ACK
START
ACK
ACK
NO
ACK _STOP
Figure 16. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 16, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 100111x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100111x1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
4.14 Status Reporting
The CS4265 has comprehensive status reporting capabilities. Many conditions can be reported in the status
register, as listed in the status register descriptions. See “Status - Address 0Dh” on page 42. Each source
may be masked off through mask register bits. In addition, each source may be set to rising edge, falling
edge, or level sensitive. Combined with the option of level-sensitive or edge-sensitive modes within the mi-
crocontroller, many different configurations are possible, depending on the needs of the equipment design-
er.
DS657F2
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