CS4244 Datasheet, PDF (48/63 Pages) Cirrus Logic – 4 In/4 Out Audio CODEC with PCM and TDM Interfaces

6.3 Clock & SP Select (Address 06h)
7
6
BASE RATE[1:0]
5
4
SPEED MODE[1:0]
3
2
1
MCLK RATE[2:0]
CS4244
0
Reserved
6.3.1
Base Rate Advisory
Advises the CS4244 of the base rate of the incoming base rate. This allows for the de-emphasis filters to
be adjusted appropriately. The CS4244 includes on-chip digital de-emphasis for 32, 44.1, and 48 kHz
base rates. It is not supported for 96 kHz or for any settings in Double Speed Mode.
BASE RATE
00
01
10
11
Base Rate is:
48 kHz
44.1 kHz
32 kHz
Reserved
6.3.2
Speed Mode
Sets the speed mode in which the CS4244 will operate..
SPEED MODE
00
01
10
11
Speed Mode is:
Single Speed Mode
Double Speed Mode
Reserved
Auto Detect (Slave Mode only)
6.3.3
Master Clock Rate
Sets the rate at which the master clock is entering the CS4244. Settings are given in “x” multiplied by the
incoming sample rate, as MCLK must scale directly with incoming sample rate.
MCLK RATE
000
001
010
011
100
101
110
111
MCLK is:
256xF_S in Single Speed Mode or 128xF_S in Double Speed Mode
384xF_S in Single Speed Mode or 192xF_S in Double Speed Mode
512xF_S in Single Speed Mode or 256xF_S in Double Speed Modex
Reserved
Reserved
Reserved
Reserved
Reserved
DS900F2
48