CS4244 Datasheet, PDF (19/63 Pages) Cirrus Logic – 4 In/4 Out Audio CODEC with PCM and TDM Interfaces

CS4244
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.
Parameters
Symbol
RST pin Low Pulse Width
(Note 25)
MCLK Frequency
(Note 26)
MCLK Duty Cycle
SCLK Duty Cycle
Input Sample Rate (FS/LRCK pin)
Single-Speed Mode F_S
Double-Speed Mode F_S
SCLK Falling Edge to SDOUTx Valid (VL = 1.8 V)
t_dh2
SCLK Falling Edge to SDOUTx Valid (VL = 2.5 V)
t_dh2
SCLK Falling Edge to SDOUTx Valid (VL = 3.3 V or 5 V)
t_dh2
TDM Slave Mode
SCLK Frequency
(Note 27)
FS/LRCK High Time Pulse
(Note 28)
t_lpw
FS/LRCK Rising Edge to SCLK Rising Edge
t_lcks
SDINx Setup Time Before SCLK Rising Edge
t_ds
SDINx Hold Time After SCLK Rising Edge
t_dh1
PCM Slave Mode
SCLK Frequency
FS/LRCK Duty Cycle
FS/LRCK Edge to SCLK Rising Edge
t_lcks
SDINx Setup Time Before SCLK Rising Edge
t_ds
SDINx Hold Time After SCLK Rising Edge
t_dh1
PCM Master Mode
SCLK Frequency
FS/LRCK Duty Cycle
FS/LRCK Edge to SCLK Rising Edge
t_lcks
SDINx Setup Time Before SCLK Rising Edge
t_ds
SDINx Hold Time After SCLK Rising Edge
(VL = 1.8 V)
t_dh1
SDINx Hold Time After SCLK Rising Edge
(VL = 2.5 V, 3.3 V, or 5 V)
t_dh1
Min
1
7.68
45
45
30
60
-
-
-
256x
1/f_SCLK
5
3
5
32x
45
5
3
5
64x
45
5
5
11
10
Max
-
25.6
55
55
50
100
31
22
17
512x
(n-1)/f_SCLK
(Note 29)
-
-
-
64x
55
-
-
-
64x
55
-
-
-
-
Units
ms
MHz
%
%
kHz
kHz
ns
ns
ns
F_S
ns
ns
ns
ns
F_S
%
ns
ns
ns
F_S
%
ns
ns
ns
ns
Notes:
25. After applying power to the CS4244, RST should be held low until after the power supplies and MCLK
are stable.
26. MCLK must be synchronous to and scale with F_S.
27. The SCLK frequency must remain less than or equal to the MCLK frequency. For this reason, SCLK
may range from 256x to 512x only in single speed mode. In double speed mode, 256x is the only ratio
supported.
28. The MSB of CH1 is always aligned with the second SCLK rising edge following FS/LRCK rising edge.
29. Where “n” is equal to the MCLK to LRCK ratio (set by the Master Clock Rate register bits), i.e. in 256x
mode, n = 256, in 512x mode, n = 512, etc.
DS900F2
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