CS4244 Datasheet, PDF (21/63 Pages) Cirrus Logic – 4 In/4 Out Audio CODEC with PCM and TDM Interfaces

CS4244
SWITCHING SPECIFICATIONS - CONTROL PORT
Test conditions (unless otherwise specified): Inputs: Logic 0 = GND = 0 V, Logic 1 = VL; SDA load capacitance equal to maxi-
mum value of C_b specified below (Note 30).
Parameters
Symbol
Min
Max Unit
SCL Clock Frequency
RESET Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Input Hold Time from SCL Falling
SDA Output Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
SDA Bus Load Capacitance
SDA Pull-Up Resistance
(Note 32)
f_scl
t_irs
t_buf
t_hdst
t_low
t_high
t_sust
t_hddi
t_hddo
t_sud
t_r
t_f
t_susp
C_b
R_p
-
(Note 31)
1.3
0.6
1.3
0.6
0.6
0
0.2
100
-
-
0.6
-
500
550
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
0.9
µs
0.9
µs
-
ns
300
ns
300
ns
-
µs
400
pF
-

Notes:
30. All specifications are valid for the signals at the pins of the CS4244 with the specified load capacitance.
31. 2 ms + (3000/MCLK). See Section 4.2.1.
32. Data must be held for sufficient time to bridge the transition time, t_f, of SCL.
RST
t _irs
Stop
Start
Repeated
Start
SDA
SCL
t _buf
t _hdst
t _high
t _hdst
tf
t _low
t _hdd
t _sud
t _sust
tr
Figure 8. I²C Control Port Timing
Stop
t _susp
DS900F2
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