CS4244 Datasheet, PDF (35/63 Pages) Cirrus Logic – 4 In/4 Out Audio CODEC with PCM and TDM Interfaces

4.6.2 ADC Path
AIN1 (±)
AIN2 (±)
AIN3 (±)
AIN4 (±)
Multi-bit
 ADC
Digital Filters
VD
2.5 VDC
VA
5.0 VDC
2.5 V
LDO
Analog Supply
Channel Volume ,
Mute, Invert,
Noise Gate
Master
Volume
Control
Interpolation
Filter
Serial Audio Interface
Level Translator
Multi-bit 
Modulators
DAC &
Analog
Filters
Control Port
CS4244
AOUT1 (±)
AOUT2 (±)
AOUT3 (±)
AOUT4 (±)
VL
1.8 to 5.0 VDC
SDOUT1 SDOUT2
SDIN2 SDIN1
Frame Sync Master Clock In Serial Clock
Clock / LRCK
In/ Out
Figure 23. ADC Path
INT RST
I²C Control
Data
4.6.2.1 Analog Inputs
AINx+ and AINx- are line-level differential analog inputs. The analog input pins do not self-bias and must
be externally biased to VA/2 to avoid clipping of the input signal. The full-scale analog input levels are
scaled according to VA and can be found in the Analog Input Characteristics tables on pages 12 and 13.
The ADC output data is in two’s complement binary format. For inputs above positive full scale or below
negative full scale, the ADC will output 7FFFFFH or 800000H, respectively, and cause the ADC Overflow
bit in the Interrupt Notification 1 register to be set to a ‘1’.
4.6.2.2 Active ADC Input Filter
The analog modulator samples the input at 6.144 MHz (internal MCLK = 12.288 MHz). The digital filter
will reject signals within the stopband of the filter. However, there is no rejection for input signals which
are multiples of the digital passband frequency (n  6.144 MHz), where n = 0,1,2,... Refer to Figure 24 for
a recommended analog input filter that will attenuate any noise energy at 6.144 MHz, in addition to pro-
viding the optimum source impedance for the modulators. The use of capacitors that have a large voltage
coefficient (such as general-purpose ceramics) must be avoided since these can degrade signal linearity.
DS900F2
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