CS4244 Datasheet, PDF (22/63 Pages) Cirrus Logic – 4 In/4 Out Audio CODEC with PCM and TDM Interfaces

4. APPLICATIONS
CS4244
4.1 Power Supply Decoupling, Grounding, and PCB Layout
As with any high-resolution converter, the CS4244 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 2 shows the recommended power ar-
rangements, with VA connected to clean supplies. VDREG, which powers the digital circuitry, is generated
internally from an on-chip regulator from the VA supply. The VDREG pin provides a connection point for the
decoupling capacitors, as shown in Figure 2.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS4244 as pos-
sible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same
side of the board as the CS4244 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+, VBIAS, and VQ pins in order to avoid unwanted coupling into the modulators.
The FILT+, VBIAS, and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize
the electrical path from their respective pins and GND.VA_SEL
For optimal heat dissipation from the package, it is recommended that the area directly under the device be
filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the back-
side ground is also recommended.
4.2 Recommended Power-up & Power-down Sequence
The initialization and Power-Up/Down sequence flow chart is shown in Figure 9. For the CS4244 Reset is
defined as all lines held static, RST line is pulled low. Power Down is defined as all lines (excluding MCLK)
held static, RST line is high, all PDNx bits are ‘1’. Running is defined as RST line high, all PDNx bits are ‘0’.
4.2.1
Power-up
The CS4244 enters a reset state upon the initial application of VA and VL. When these power supplies
are initially applied to the device, the audio outputs, AOUTxx, are clamped to VQ which is initially low.
Additionally, the interpolation and decimation filters, delta-sigma modulators and control port registers are
all reset and the internal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and
low-pass filters are powered down. The device remains in the reset state until the RST pin is brought high.
Once RST is brought high, the control port address is latched after 2 ms + (3000/MCLK). Until this latching
transition is complete, the device will not respond to I²C reads or writes, but the I²C bus may still be used
during this time. Once the latching transition is complete, the address is latched and the control port is
accessible. At this point and the desired register settings can be loaded per the interface descriptions de-
tailed in the Section 4.3 I²C Control Port. To ensure specified performance and timing, the VA_SEL must
be set to “0” for VA = 3.3 VDC and “1” for VA = 5.0 VDC before audio output begins.
After the RST pin is brought high and MCLK is applied, the outputs begin to ramp with VQ towards the
nominal quiescent voltage. VQ will charge to VA/2 upon initial power up. The time that it takes to charge
up to VA/2 is governed by the size of the capacitor attached to the VQ pin. With the capacitor value shown
in the typical connection diagram, the charge time will be approximately 250 ms. The gradual voltage
ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the qui-
escent DC voltage. Once FS/LRCK is valid, MCLK occurrences are counted over one F_S period to deter-
mine the MCLK/F_S ratio. With MCLK valid and any of the PDNx bits cleared, the internal voltage
references will transition to their nominal voltage. Power is applied to the D/A converters and filters, and
the analog outputs are un-clamped from the quiescent voltage, VQ. Afterwards, normal operation begins.
DS900F2
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