CS4244 Datasheet, PDF (26/63 Pages) Cirrus Logic – 4 In/4 Out Audio CODEC with PCM and TDM Interfaces

4.3.1
CS4244
Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudocode above for implementation details.
4.3.1.1 Map Increment (INCR)
The CS4244 has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR
is set to ‘0’, MAP will stay constant for successive I²C reads or writes. If INCR is set to ‘1’, MAP will auto-
increment after each byte is read or written, allowing block reads or writes of successive registers.
4.4 System Clocking
The CS4244 will operate at sampling frequencies from 30 kHz to 100 kHz. This range is divided into two
speed modes as shown in Table 1.
Mode
Single-Speed
Double-Speed
Sampling Frequency
30-50 kHz
60-100 kHz
Table 1. Speed Modes
The serial port clocking must be changed while all PDNx bits are set. If the clocking is changed otherwise,
the device will enter a mute state, see Section 4.8 on page 43.
4.4.1 Master Clock
The ratio of the MCLK frequency to the sample rate must be an integer. The FS/LRCK frequency is equal
to F_S, the frequency at which all of the slots of the TDM stream or channels in Left Justified or I²S formats
are clocked into or out of the device. The Speed Mode and Master Clock Rate bits configure the device
to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. Table 2 illus-
trates several standard audio sample rates and the required MCLK and FS/LRCK frequencies.
The CS4244 has an internal fixed ratio PLL. This PLL is activated when the “MCLK RATE[2:0]” bits in the
"Clock & SP Sel." register are set to either 000 or 001, corresponding to 256x or 384x. When in either of
these two modes, the PLL will activate to adjust the frequency of the incoming MCLK to ensure that the
internal state machines operate at a nominal 24.576 MHz rate. As is shown in the Typical Current Con-
sumption table, activation of the PLL will increase the power consumption of the CS4244.
FS/LRCK (kHz)
32
44.1
48
64
88.2
96
Mode
128x
(Note 33)
-
-
-
8.1920
11.2896
12.2880
192x
(Note 33)
-
-
-
12.2880
16.9344
18.4320
DSM
MCLK (MHz)
256x
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
Table 2. Common Clock Frequencies
Note:
33. 128x and 192x ratios valid only in Left Justified or I²S formats.
DS900F2
384x
512x
12.2880
16.3840
16.9344
22.5792
18.4320
24.5760
-
-
-
-
-
-
SSM
26