CS4244 Datasheet, PDF (27/63 Pages) Cirrus Logic – 4 In/4 Out Audio CODEC with PCM and TDM Interfaces

4.4.2
CS4244
Master Mode Clock Ratios
As a clock master, FS/LRCK and SCLK will operate as outputs internally derived from MCLK. FS/LRCK
is equal to F_S and SCLK is equal to 64x F_S as shown in Figure 13. TDM format is not supported in Master
Mode.
MCLK
MCLK Rate Bits
x2
000
÷ 1.5
x2
001
÷1
010
PLL active
÷ 512
00
÷ 256
01
Speed Mode Bits
÷8
00
÷4
01
FS /LRCK
SCLK
Figure 13. Master Mode Clocking
4.4.3
The resulting valid master mode clock ratios are shown in Table 3 below.
MCLK/F_S
SCLK/F_S
SSM
256x, 384x, 512x
64x
DSM
128x, 192x, 256x
64x
Table 3. Master Mode Left Justified and I²S Clock Ratios
Slave Mode Clock Ratios
In Slave Mode, SCLK and FS/LRCK operate as inputs. The FS/LRCK clock frequency must be equal to
the sample rate, F_S, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
512x, 256x, 128x, 64x, 48x or 32x F_S, depending on the desired format and speed mode. Refer to Table 4
and Table 5 for required clock ratios.
MCLK/F_S
SCLK/F_S
SSM
256x, 384x, 512x
32x, 48x, 64x, 128x
DSM
128x, 192x, 256x
32x, 48x, 64x
Table 4. Slave Mode Left Justified and I²S Clock Ratios
(Note 34)
MCLK/F_S
SCLK/F_S
SSM
256x, 384x, 512x
256x
512x
512x
Table 5. Slave Mode TDM Clock Ratios
DSM
256x
256x
Note:
34. For all cases, the SCLK frequency must be less than or equal to the MCLK frequency.
DS900F2
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