EP7312 Datasheet, PDF (6/64 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

EP7312
High-Performance, Low-Power System on Chip
Description of the EP7312’s Components, Functionality, and Interfaces
The following sections describe the EP7312 in more
detail.
Processor Core - ARM720T
The EP7312 incorporates an ARM 32-bit RISC micro
controller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key
features include:
• ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
• Enhanced MMU for Microsoft Windows CE and other
operating systems
• 8 KB of 4-way set-associative cache.
• Translation Look Aside Buffers with 64 Translated
Entries
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7312 through the use of laser
probing technology. These IDs can then be used to match
secure copyrighted content with the ID of the target
device the EP7312 is powering, and then deliver the
copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
Memory Interfaces
Power Management
The EP7312 is designed for ultra-low-power operation.
Its core operates at only 2.5 V, while its I/O has an
operation range of 2.5 V–3.3 V. The device has three basic
power states:
• Operating — This state is the full performance
state. All the clocks and peripheral logic are
enabled.
• Idle — This state is the same as the Operating
State, except the CPU clock is halted while
waiting for an event such as a key press.
• Standby — This state is equivalent to the
computer being switched off (no display), and
the main oscillator shut down. An event such as
a key press can wake-up the processor.
Table 1 shows the power management pin assignments.
Table 1. Power Management Pin Assignments
There are two main external memory interfaces. The first
one is the ROM/SRAM/FLASH-style interface that has
programmable wait-state timings and includes burst-
mode capability, with six chip selects decoding six
256 MB sections of addressable space. For maximum
flexibility, each bank can be specified to be 8-, 16-, or 32-
bits wide. This allows the use of 8-bit-wide boot ROM
options to minimize overall system cost. The on-chip
boot ROM can be used in product manufacturing to
serially download system code into system FLASH
memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-
leading code density. shows the Static Memory Interface
pin assignments.
Table 2. Static Memory Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
Pin Mnemonic
BATOK
nEXTPWR
I/O
Pin Description
I
Battery ok input
I
External power supply sense
input
nCS[5:0]
A[27:0]
D[31:0]
nMOE/nSDCAS
(Note)
O Chip select out
O Address output
I/O Data I/O
O ROM expansion OP enable
nPWRFL
I
Power fail sense input
nMWE/nSDWE
(Note) O ROM expansion write enable
nBATCHG
I
Battery changed sense input
HALFWORD
O
Halfword access select
output
MaverickKey^™ Unique ID
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
WORD
WRITE/nSDRAS
(Note)
O Word access select output
O Transfer direction
Note: Pins are multiplexed. See Table 19 on page 11 for
more information.
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©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
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