EP7312 Datasheet, PDF (25/64 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

Static Memory Burst Write Cycle
EP7312
High-Performance, Low-Power System on Chip
EXPCLK
nCS
A
nMWE
nMOE
HALF
WORD
WORD
D
EXPRDY
t_CSd
t_Ad
t_MWd
t_HWd
t_WDd
t_Dv
t_EXs
t_Ah
t_Ah
t_Ah
t_CSh
t_MWh
t_MWd
t_MWh
t_MWd
t_MWh
t_MWd
t_MWh
t_Dnv
t_Dv t_Dnv
t_Dv t_Dnv
t_Dv
t_EXh
WRITE
Figure 10. Static Memory Burst Write Cycle Timing Measurement
Note:
1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.
DS508PP5
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
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