EP7312 Datasheet, PDF (22/64 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

EP7312
High-Performance, Low-Power System on Chip
Static Memory Single Read Cycle
EXPCLK
nCS
A
nMWE
nMOE
HALF-
WORD
WORD
D
EXPRDY
WRITE
t_CSd
t_Ad
t_CSh
t_HWd
t_WDd
t_MOEd
t_EXs
t_WRd
t_MOEh
t_Ds
t_Dh
t_EXh
Figure 7. Static Memory Single Read Cycle Timing Measurement
Note:
1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Address, Halfword, Word, and Write hold state until next cycle.
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©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS508PP5