EP7312 Datasheet, PDF (55/64 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

DS508PP5
EP7312
High-Performance, Low-Power System on Chip
Table 23. JTAG Boundary Scan Signal Ordering (Continued)
LQFP TFBGA PBGA
Pin No. Ball
Ball
Signal
Type Position
8
C2
D2
9
E2
F4
10
D2
E1
13
F3
E2
14
D1
G5
15
F2
F1
16
E1
G4
17
F1
F2
18
G2
H7
19
G1
G1
20
H3
H6
23
H1
H1
24
J3
H5
25
J2
H2
26
J1
H4
27
L3
J1
28
K2
J4
29
K1
J2
30
M3
J5
31
L2
K1
32
L1
J6
34
N3
K2
35
M2
J7
36
M1
L1
37
P3
K4
38
N1
L2
39
N2
K5
40
R3
M1
41
P1
K6
42
P2
M2
43
T3
L4
44
R1
N1
45
R2
L5
46
T1
N2
47
T2
M4
53
V4
T2
54
W4
T3
55
Y4
N5
EXPRDY
TXD2
RXD2
PB[7]
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]
PB[0]
PA[7]
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
PA[0]
LEDDRV
TXD1
PHDIN
CTS
RXD1
DCD
DSR
nTEST1
nTEST0
EINT3
nEINT2
nEINT1
nEXTFIQ
PE[2]/CLKSEL
PE[1]/
BOOTSEL[1]
PE[0]/BOOTSEL0
PD[7]/SDQM[1]
PD[6/SDQM[0]]
PD[5]
I
13
O
14
I
16
I/O
17
I/O
20
I/O
23
I/O
26
I/O
29
I/O
32
I/O
35
I/O
38
I/O
41
I/O
44
I/O
47
I/O
50
I/O
53
I/O
56
I/O
59
I/O
62
O
65
O
67
I
69
I
70
I
71
I
72
I
73
I
74
I
75
I
76
I
77
I
78
I
79
I/O
80
I/O
83
I/O
86
I/O
89
I/O
92
I/O
95
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
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