EP7312 Datasheet, PDF (42/64 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

EP7312
High-Performance, Low-Power System on Chip
Ball Location
Name
C20
nPOR
D1
PB[7]
D2
RXD[2]
D3
VDDIO
D18
VSSIO
D19
nBATCHG
D20
A[7]
E1
PB[4]
E2
TXD[2]
E3
WRITE/nSDRAS
E18
nMEDCHG/nBROM
E19
nEXTPWR
E20
D[9]
F1
PB[3]
F2
PB[6]
F3
TDI
F18
D[7]
F19
A[8]
F20
D[10]
G1
PB[1]
G2
PB[2]
G3
PB[5]
G18
D[8]
G19
A[9]
G20
D[11]
H1
PA[7]
H[2]
TDO
H[3]
H[18]
H19
H20
J1
PB[0]
A[10]
D[12]
A[12]
PA[4]
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Strength^†
Schmitt
1
Reset
State
Input^‡
1
Low
1
Input^‡
1
High
1
Low
1
1
1
with p/u*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Low
Input^‡
Input^‡
Low
Low
Low
Input^‡
Input^‡
Input^‡
Input^‡
Low
Low
Input^‡
Input^‡
Input^‡
Low
Low
Low
Input^‡
Type
I
I
I
Pad power
Pad ground
I
O
I
O
O
I
I
I/O
I/O
I/O
I
I/O
O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
O
I/O
O
I/O
O
I/O
Description
Power-on reset input
GPIO port B
UART 2 receive data input
Digital I/O power, 3.3V
I/O ground
Battery changed sense input
System byte address
GPIO port B
UART 2 transmit data output
Transfer direction / SDRAM RAS signal output
Media change interrupt input / internal ROM boot enable
External power supply sense input
Data I/O
GPIO port B
GPIO port B
JTAG data input
Data I/O
System byte address
Data I/O
GPIO port B
GPIO port B
Data I/O
System byte address
Data I/O
GPIO port A
JTAG data out
GPIO port B
System byte address
Data I/O
System byte address
GPIO port A
42
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS508PP5