EP7312 Datasheet, PDF (44/64 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

EP7312
High-Performance, Low-Power System on Chip
Ball Location
Name
P20
D[20]
R1
nEXTFIQ
R2
PE[2]/CLKSEL
R3
nTEST[0]
R18
A[19]/DRA[8]
R19
D[22]
R20
A[21]/DRA[6]
T1
PE[1]/BOOTSEL[1]
T2
PE[0]/BOOTSEL[0]
T3
nEINT[1]
T18
D[21]
T19
D[23]
T20
A[22]/DRA[5]
U1
VSSRTC
U2
RTCOUT
U3
RTCIN
U18
HALFWORD
U19
D[24]
U20
A[23]/DRA[4]
V1
VDDRTC
V2
VSSIO
V3
VSSIO
V4
PD[7]/SDQM[1]
V5
PD[4]
V6
PD[2]
V7
SSICLK
V8
SSIRXDA
V9
nADCCS
V10
VDDIO
V11
ADCCLK
V12
COL[7]
V13
COL[4]
V14
TCLK
V15
BUZ
V16
D[29]
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Strength^†
1
Reset
State
Low
1
With p/u*
1
1
1
1
1
Input^‡
Low
Low
Low
Input^‡
Input^‡
1
Low
1
Low
1
Low
1
Low
1
Low
1
Low
1
Low
1
Low
1
Low
1
Input^‡
1
High
1
Low
1
High
1
High
1
Low
1
Low
Type
I/O
I
I/O
I
O
I/O
O
I/O
I/O
I
I/O
I/O
O
RTC ground
O
I/O
O
I/O
O
RTC power
Pad ground
Pad ground
I/O
I/O
I/O
I/O
I/O
O
Pad power
O
O
O
I
O
I/O
Description
Data I/O
External fast interrupt input
GPIO port E / clock input mode select
Test mode select input
System byte address / SDRAM address
Data I/O
System byte address / SDRAM address
GPIO port E / boot mode select
GPIO port E / boot mode select
External interrupt input
Data I/O
Data I/O
System byte address / SDRAM address
Real time clock ground
Real time clock oscillator output
Real time clock oscillator input
Halfword access select output
Data I/O
System byte address / SDRAM address
Real time clock power, 2.5V
I/O ground
I/O ground
GPIO port D / SDRAM byte lane mask
GPIO port D
GPIO port D
DAI/CODEC/SSI2 serial clock
DAI/CODEC/SSI2 serial data input
SSI1 ADC chip select
Digital I/O power, 3.3V
SSI1 ADC serial clock
Keyboard scanner column drive
Keyboard scanner column drive
JTAG clock
Buzzer drive output
Data I/O
44
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(All Rights Reserved)
DS508PP5