SMJ44C251B Datasheet, PDF (9/57 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
FIGURE 1: EXAMPLE OF WRITE-PER-BIT OPERATIONS
DQ Mask = H: Write to I/O enable
= L: Write to I/O disable
FIGURE 2: EXAMPLE BLOCK-WRITE DIAGRAM OPERATIONS
NOTES:
* W\ must be low during the block-write cycle.
DQ0–DQ3 are latched on the later of W\ or CAS\ falling edge except in block 6 (see legend).
LEGEND:
1. Refresh address
2. Row address
3. Block address (A2 –A8)
4. Color-register data
5. Column-mask data
6. DQ-mask data. DQ0–DQ3 are latched on the falling edge of RAS\.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
9
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