SMJ44C251B Datasheet, PDF (4/57 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
FUNCTION TABLE
FUNCTION
CBR Refresh
Register-to-memory transfer
(transfer write)
Alternate transfer write
(independent of SE\)
Serial-write-mode enable
(pseudo-transfer write)
Memory-to-register transfer
(transfer read)
Split-register-transfer read
(must reload tap)
Load and use write mask,
Write data to DRAM
Load and use write mask,
Block write to DRAM
Persistent write-per-bit,
Write data to DRAM
Persistent write-per-bit,
Block write to DRAM
Normal DRAM read/write
(nonmasked)
Block write to DRAM
(nonmasked)
Load write mask
Load color register
RAS\ FALL
CAS\ TRG\ _W\¹
L
X
X
H
L
L
DSF
X
X
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
H
H
L
L
L
H
H
L
L
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
CAS\
FALL
ADDRESS
SE\ DSF RAS\ CAS\
DQ0 - DQ3
RAS\ ^{CAS\2 TYPE3}
W\
X
X
X
X
X
X
R
L
X
Row
Addr
Tap
Point
X
X
T
X
X
Row
Addr
Tap
Point
X
X
T
H
X
Refresh Tap
Addr Point
X
X
T
X
X
Row
Addr
Tap
Point
X
X
T
X
X
Row
Addr
Tap
Point
X
X
T
X
L
Row
Addr
Col
Addr
DQ Valid
Mask Data
R
X
H
Row Blk Addr DQ Col
Addr A2-A8 Mask Mask
R
X
L
Row
Addr
Col
Addr
X
Valid
Data
R
X
H
Row Blk Addr
Addr A2-A8
X
Col
Mask
R
X
L
Row
Addr
Col
Addr
X
Valid
Data
R
X
H
Row Blk Addr
Addr A2-A8
X
Col
Mask
R
X
L
Refresh
Addr
X
X
DQ
Mask
R
X
H
Refresh
Addr
X
X
Color
Data
R
NOTES:
1. In persistent write-per-bit function, W\ must be high during the refresh cycle.
2. DQ0 - DQ3 are latched on the later of W\ or CAS\ falling edge. Col Mask = H: Write to address/column location enabled.
DQ Mask = H: Write to I/O enabled.
3. R = random access operation, T = transfer operation.
LEGEND
H = HIGH
L = LOW
X = Don’t Care
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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