SMJ44C251B Datasheet, PDF (7/57 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
RANDOM-ACCESS-OPERATION FUNCTIONS
FUNCTION
RAS\ FALL
CAS\ TRG\ _W\¹ DSF
CAS\
FALL
SE\ DSF
ADDRESS
RAS\ CAS\
CBR Refresh
Load and use write mask,
Write data to DRAM
Load and use write mask,
Block write to DRAM
Persistent write-per-bit,
Write data to DRAM
Persistent write-per-bit,
Block write to DRAM
Normal DRAM read/write
(nonmasked)
Block write to DRAM
(nonmasked)
Load write mask
Load color register
L
X
X
X
X
X
X
X
H
H
L
L
X
L
Row
Addr
Col
Addr
H
H
L
L
X
H
Row Blk Addr
Addr A2-A8
H
H
L
H
X
L
Row
Addr
Col
Addr
H
H
L
H
X
H
Row Blk Addr
Addr A2-A8
H
H
H
L
X
L
Row
Addr
Col
Addr
H
H
H
L
X
H
Row Blk Addr
Addr A2-A8
H
H
H
H
X
L
Refresh
Addr
X
H
H
H
H
X
H
Refresh
Addr
X
DQ0 - DQ3
RAS\
X
DQ
Mask
DQ
Mask
X
X
X
X
X
X
CAS\²
W\
X
Valid
Data
Col
Mask
Valid
Data
Col
Mask
Valid
Data
Col
Mask
DQ
Mask
Color
Data
NOTES:
1. In persistent write-per-bit function, W must be high during the refresh cycle.
2. DQ0–DQ3 are latched on the later of W or CAS falling edge. Col Mask = H: Write to address/column location enabled.
DQ Mask = H: Write to I/O enabled
LEGEND:
H = High
L = Low
X = Don’t care
RANDOM-ACCESS OPERATION
The random-access operation functions are summarized in
the “Random-Access-Operation Function” table and described
in the following sections.
row-address hold time has been satisfied, usually well in ad-
vance of the falling edge of CAS\. In this case, data can be
obtained after t_a(C) max (access time from CAS low), if t_a(CA) max
(access time from column address) has been satisfied.
ENHANCED PAGE-MODE
Enhanced page-mode operation allows faster memory
access by keeping the same row address while selecting
random column addresses. This mode eliminates the time
required for row address setup-and-hold and address
multiplex. The maximum RAS\ low time and the CAS\ page cycle
time used determine the number of columns that can be
accessed.
Unlike conventional page-mode operation, the enhanced
page mode allows the SMJ44C251B/MT42C4256 to operate at a
higher data bandwidth. Data retrieval begins as soon as the
column address is valid rather than when CAS\ transitions low.
A valid column address can be presented immediately after
REFRESH
There are three types of refresh available on the
SMJ44C251B/MT42C4256: RAS\-only refresh, CBR refresh, and
hidden refresh.
RAS\-ONLY REFRESH
A refresh operation must be performed to each row at least
once every 8 ms to retain data. Unless CAS\ is applied, the
output buffers are in the high-impedance state, so the RAS\-
only refresh sequence avoids any output during refresh. Exter-
nally generated addresses must be supplied during RAS-only
refresh. Strobing each of the 512 row addresses with RAS causes
(continued)
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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