SMJ44C251B Datasheet, PDF (45/57 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
FIGURE 35: Split-Register-Transfer Operating Sequence
NOTES:
NOTE Q: In order to achieve proper split-register operation, a normal read transfer should be performed before the first split-register transfer cycle.
This is necessary to initialize the data register and the starting tap location. First serial access can then begin either after the normal read-transfer
cycle (CASE I), during the first split-register cycle (CASE II), or even after the first split-register transfer cycle (CASE III). There is no minimum
requirement of SC clock between the normal read-transfer cycle and the first split-register cycle.
NOTE R: A split register transfer into the inactive half is not allowed until t_d(MSRL) is met. t_d(MSRL) is the minimum delay time between the rising edge
of the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS\ of the split-register transfer cycle into the inactive half. After t_d(MSRL)
is met, the split-register transfer into the inactive half must also satisfy the t_d(RHMS) requirement. t_d(RHMS) is the minimum delay time between the
rising edge of RAS\ of the split-register transfer cycle into the inactive half and the rising edge of the serial clock of the last bit (bit 255 or 511). There
is a minimum requirement of one rising edge of SC clock between two split-register transfer cycles.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
45
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