SMJ44C251B Datasheet, PDF (21/57 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
TIMING REQUIREMENTS (continued)¹
PARAMETER
Delay time, TRG\ high before data applied at DQ
Delay time, RAS\ low to TRG\ high
(real-time-reload read-transfer cycle only)
Delay time, RAS\ low to first SC high after
TRG\ high¹⁴
Delay time, CAS\ low to first SC high after TRG\
high¹⁴
Delay time, SC high to TRG\ high^14,15,16
Delay time, TRG\ high to RAS\ high^15,16
Delay time, SC high to RAS\ low with
TRG\ = W\ = low^{6, 17, 18}
Delay time, SC high to SE\ high in serial-input
mode
Delay time, RAS\ high to SC high⁶
Delay time, TRG\ high to RAS\ low¹⁹
Delay time, TRG\ high to SC high^{15, 16}
Delay time, SE\ low to SC high²⁰
Delay time, RAS\ high to last (most significant)
rising edge of SC before boundary switch during
split-register read-transfer cycles
Delay time, CAS\ low to TRG\ high in real-time
read-transfer cycles
Delay time, column address to first SC in early-
load read-transfer cycles
Delay time, column address to TRG\ high in real-
time read-transfer cycles
Delay time, RAS\ low to column address¹²
SYM/ALT. SYM
t_d(GHD)/t_OED
-10
MIN MAX
25
t_d(RLTH)/t_RTH
90
t_d(RLSH)/t_RSD 130
t_d(CLSH)/t_CSD
40
t_d(SCTR)/t_TSL
15
t_d(THRH)/t_TRD
-10
t_d(SCRL)/t_SRS
10
t_d(SCSE)
t_d(RHSC)/t_SRD
t_d(THRL)/t_TRP
t_d(THSC)/t_TSD
t_d(SESC)/t_SWS
20
25
t_w(RH)
35
10
t_d(RHMS)
15
t_d(CLGH)/t_CTH
5
t_d(CASH)/t_ASD
45
t_d(CAGH)/t_ATH
10
t_d(RLCA)/t_RAD
15
50
Delay time, data to CAS\ low
t_d(DCL)/t_DZC
0
Delay time, data to TRG\ low
t_d(DGL)/t_DZO
0
Delay time, RAS\ low to serial-input data
t_d(RLSD)/t_SDD
50
Delay time, TRG\ low to RAS\ high
t_d(GLRH)/t_ROH
25
Delay time, last (most significant) rising edge of
SC to RAS\ low before boundary switch during
split-register read-transfer cycles
t_d(MSRL)
25
Delay time, last (255 or 511) rising edge of SC to
QSF switching a the boundary during split-register _{td(SCQSF)/tSQD}
40
read transfer cycles²¹
Delay time, CAS\ low to QSF switching in read-
transfer or write-transfer cycles²¹
t_d(CLQSF)/t_CQD
35
Delay time, TRG\ high to QSF switching in read-
transfer or write-transfer cycles²¹
t_d(GHQSF)/t_TQD
30
Delay time, RAS\ low to QSF switching in read-
transfer or write-transfer cycles²¹
t_d(RLQSF)/t_RQD
75
Refresh time interval, memory
t_rf /t_REF
8
Transition time
t_t/t_T
3
50
-12
MIN MAX
30
UNIT
ns
95
ns
140
ns
45
ns
20
ns
-10
ns
20
ns
20
ns
30
ns
t_w(RH)
ns
40
ns
15
ns
20
ns
5
ns
50
ns
10
ns
15
60
ns
0
ns
0
ns
50
ns
30
ns
25
ns
40
ns
35
ns
30
ns
75
ns
8
ms
3
50
ns
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
21
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.