SMJ44C251B Datasheet, PDF (41/57 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
FIGURE 31: Memory-to-Data-Register Transfer-Cycle Timing,
Early-Load Operation
NOTES:
NOTE H: Early-load operation is defined as t_h(TRG) min < t_h(TRG) < t_d(RLTH) min.
NOTE I: DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written from the 512
corresponding columns of the selected row. The data that is transferred into the data registers can be either shifted out or transferred back into another
row.
NOTE J: Once data is transferred into the data registers, the SAM is in the serial-read mode (i.e., SQ is enabled), allowing data to be shifted out of the
registers. Also, the first bit to be read from the data register after TRG\ has gone high must be activated by a positive transition of SC.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
41
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