SMJ44C251B Datasheet, PDF (28/57 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
FIGURE 18: Enhanced-Page-Mode Write-Cycle Timing
NOTES:
1. Referenced to CAS or W, whichever occurs last
NOTE B: A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing specifications.
TRG\ must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late-write feature is used. If the early-write-
cycle timing is used, the state of TRG\ is a don’t care after the minimum period t_h(TRG) from the falling edge of RAS\.
WRITE-CYCLE STATE TABLE
CYCLE
1
Write Operation
L
Write-mask load/use, Write DQs to I/Os
L
Use previous write mask, Write DQs to I/Os
H
Load write mask on later of W\ fall and CAS\ fall H
STATE
2
3
4
5
L
H
Don't Care Valid Data
L
L Write Mask Valid Data
L
L
Don't Care Valid Data
L
H
Don't Care Write Mask
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
28
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