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SMJ44C251B Datasheet, PDF (2/57 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM
Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
DESCRIPTION
The SMJ44C251B/MT42C4256 multiport video RAM is a
high-speed, dual-ported memory device. It consists of a
dynamic random-access memory (DRAM) organized as 262144
words of 4 bits each interfaced to a serial-data register or serial-
access memory (SAM) organized as 512 words of 4 bits each.
The SMJ44C251B/MT42C4256 supports three types of
operation: random access to and from the DRAM, serial access
to and from the serial register, and bidirectional transfer of data
between any row in the DRAM and the serial register. Except
during transfer operations, the SMJ44C251B/MT42C4256 can
be accessed simultaneously and asynchronously from the
DRAM and SAM ports.
During a transfer operation, the 512 columns of the DRAM
are connected to the 512 positions in the serial data register.
The 512 × 4-bit serial-data register can be loaded from the
memory row (transfer read), or the contents of the 512 × 4-bit
serial-data register can be written to the memory row (transfer
write).
The SMJ44C251B/MT42C4256 is equipped with several
features designed to provide higher system-level bandwidth
and to simplify design integration on both the DRAM and SAM
ports. On the DRAM port, greater pixel draw rates can be
achieved by the device’s 4 × 4 block-write mode. The block-
write mode allows four bits of data (present in an on-chip color-
data register) to be written to any combination of four adjacent
column-address locations. As many as 16 bits of data can be
written to memory during each CAS cycle time. Also on the
DRAM port, a write mask or a write-per-bit feature allows mask-
ing any combination of the four input/outputs on any write
cycle. The persistent write-per-bit feature uses a mask register
that, once loaded, can be used on subsequent write cycles. The
mask register eliminates having to provide mask data on every
mask-write cycle.
The SMJ44C251B/MT42C4256 offers a split-register
transfer read (DRAM to SAM) feature for the serial tester (SAM
port). This feature enables real-time register reload
implementation for truly continuous serial data streams without
critical timing requirements. The register is divided into a high
half and a low half. While one half is being read out of the SAM
port, the other half can be loaded from the memory array. For
applications not requiring real-time register reload (for example,
reloads done during CRT retrace periods), the single-register
mode of operation is retained to simplify design. The SAM can
also be configured in input mode, accepting serial data from an
external device. Once the serial register within the SAM is
loaded, its contents can be transferred to the corresponding
column positions in any row in memory in a single memory
cycle.
The SAM port is designed for maximum performance. Data
can be input to or accessed from the SAM at serial rates up to
33 MHz. During the split-register mode of operation, internal
circuitry detects when the last bit position is accessed from the
active half of the register and immediately transfers control to
the opposite half. A separate output, QSF, is included to
indicate which half of the serial register is active at any given
time in the split-register mode.
All inputs, outputs, and clock signals on the SMJ44C251B/
MT42C4256 are compatible with Series 54 TTL devices. All ad-
dress lines and data-in lines are latched on-chip to simplify
system design. All data-out lines are unlatched to allow greater
system flexibility.
Enhanced page-mode operation allows faster memory
access by keeping the same row address while selecting
random column addresses. The time for row-address setup,
row-address hold, and address multiplex is eliminated, and a
memory cycle time reduction of up to 3× can be achieved,
compared to minimum RAS cycle times. The maximum number
of columns that can be accessed is determined by the maximum
RAS low time and page-mode cycle time used. The
SMJ44C251B/MT42C4256 allows a full page (512 cycles) of
information to be accessed in read, write, or read-modify-write
mode during a single RAS-low period using relatively conser-
vative page-mode cycle times.
The SMJ44C251B/MT42C4256 employs state-of-the-art
technology for very high performance combined with improved
reliability.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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