SMJ44C251B Datasheet, PDF (34/57 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
FIGURE 24: Enhanced-Page-Mode
Block-Write-Cycle Timing
NOTES:
1. Referenced to CAS\ or W\, whichever occurs last
NOTE D: TRG\ must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late write feature is used. If
the early-write-cycle timing is used, the state of TRG\ is a don’t care after the minimum period t_h(TRG) from the falling edge of RAS\.
ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE STATE TABLE
CYCLE
STATE
1
2
3
4
Write-mask load/use, Block write
L
L Write Mask Column Mask
Use previous write mask, Block write
H
L
Don't Care Column Mask
Write mask disable, Block write to all I/Os
L
Write mask data 0: I/O write disable
1: I/O write enable
Column mask data DQn =
0 column write disable
(n = 0, 1, 2, 3) 1 column write enable
H
Don't Care Column Mask
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
34
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