PS-AT65609EHW Datasheet, PDF (20/30 Pages) ATMEL Corporation – MICROCIRCUIT, DIGITAL, MEMORY, 8K x 8-Bit, 5V Very Low Power CMOS SRAM, MONOLITHIC SILICON

PS-AT65609EHW
Rev A
6.3.3 Data Retention Mode
Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and supply
current are guaranteed over temperature. The following rules ensure data retention:
1. During data retention chip select CS1 must be held high within VCC to VCC -0.2V or, chip
select CE must be held down within GND to GND +0.2V.
2. Output Enable ( OE ) should be held high to keep the RAM outputs high impedance,
minimizing power dissipation.
3. During power up and power-down transitions CS1 and OE must be kept between VCC +
0.3V and 70% of VCC, or with CE between GND and GND -0.3V.
4. The RAM can begin operation > TR ns after VCC reaches the minimum operation voltages
(4.5V).
FIGURE 2 - Data retention timing waveform
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