PS-AT65609EHW Datasheet, PDF (12/30 Pages) ATMEL Corporation – MICROCIRCUIT, DIGITAL, MEMORY, 8K x 8-Bit, 5V Very Low Power CMOS SRAM, MONOLITHIC SILICON

PS-AT65609EHW
Rev A
NOTES
1) Functional go-no-go test with the following test sequences :
FUNCTIONAL TEST 1
Pattern
Timing
VCC
VSS
VIL
VIH
IOL
IOH Vout comp
(ns) (a,c)
(V)
(V)
(V)
(V)
(mA)
(mA)
(V)
March
105
4.5-5.5
0
0
3
0.5
-0.5
1.5
Checkerboard
105
4.5-5.5
0
0
3
0.5
-0.5
1.5
Imag
105
4.5-5.5
0
0
3
0.5
-0.5
1.5
Genbl
105
4.5
0
0
3
0.5
-0.5
1.5
FUNCTIONAL TEST 2
Pattern
March
March
March
March
Timing
VCC
VSS
VIL
VIH
IOL
IOH Vout comp
(ns) (a,c)
(V)
(V)
(V)
(V)
(mA)
(mA)
(V)
105
6
0
-0.3
6.3
0.5
-0.5
1.5
105
4
0
-0.3
4.3
0.5
-0.5
1.5
105
5.5
0
0
2.2
0.5
-0.5
1.5
105
4.5
0
0.8
0
0.5
-0.5
1.5
FUNCTIONAL TEST 3
Pattern
March
Timing
VCC
VSS
VIL
VIH
IOL
IOH Vout comp
(ns) (a,c)
(V)
(V)
(V)
(V)
(mA)
(mA)
(V)
105
4.5
0
0
3
8
-4
(b)
FUNCTIONAL TEST 4
Pattern
March
Comarch
Imag
Checkerboard
Timing
VCC
(ns) (a,c)
(V)
100 4.5 and 5.5V
100 4.5 and 5.5V
100 4.5 and 5.5V
100 4.5 and 5.5V
VSS
(V)
0
0
0
0
VIL
VIH
(V)
(V)
0
3
0
3
0
3
0
3
IOL
(mA)
0.5
0.5
0.5
0.5
IOH
(mA)
-0.5
-0.5
-0.5
-0.5
Vout comp
(V)
1.5
1.5
1.5
1.5
a) a write cycle is followed by a read cycle. The time between start of write and start of read per the truth table
is the specified “timing” parameter. t_r = t_f = 5 ns maximum
b) 0.4V for low output level, 2.4V for high output level
c) Ouput load 1 TTL gate equivalent + C_L < 30 pF
2) Select address inputs to produce a low level at the pin under test.
3) Select address inputs to produce a high level at the pin under test.
4) Measurements are performed with the memory loaded with a background of zeros, then with a
background of ones, for all inputs high, then low. Only the worst case is recorded.
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