TMD2725 Datasheet, PDF (32/50 Pages) ams AG – The device features advanced proximity measurement

TMD2725 − RegisterDescription
Figure 46:
CFG3 Register
CFG3 Register (Address 0xAB)
Addr: 0xAB
CFG3
Bit
Bit Name Default Access
Bit Description
7
INT_READ_CLEAR
0
6:5
Reserved
0x2
If the Interrupt-Clear-by-Read bit is set, then all flag
RW
bits in the STATUS register will be reset whenever
the STATUS register is read over I²C.
RW
Reserved
The Sleep After Interrupt bit is used to place the
device into a low power mode upon an interrupt pin
assertion.
4
SAI
PON
SAI
INT
Oscillator
0
RW
0
X
X
OFF
1
0
X
ON
1
1
1
ON
1
1
0
OFF
3:0
Reserved
0xC
RW
Reserved
The SAI bit sets the device operational mode following the
completion of an ALS or proximity cycle. If AINT and AIEN are
both set or if PINT and PIEN are both set, causing an interrupt
on the INT pin, and the SAI bit is set, then the oscillator will
deactivate. The Device will appear as if PON = 0, however, PON
will read as 1. The device can only be reactivated (oscillator
enabled) by clearing the interrupts in the STATUS register.
Page 32
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ams Datasheet
[v1-11] 2016-Sep-20