TMD2725 Datasheet, PDF (12/50 Pages) ams AG – The device features advanced proximity measurement

Figure 17:
I²C Timing
TMD2725 − Detailed Description
I²C Write Transaction
A Write transaction consists of a START, CHIP-ADDRESS WRITE,
REGISTER-ADDRESS, DATA BYTE(S), and STOP. Following each
byte (9TH clock pulse) the slave places an ACKNOWLEDGE/
NOT-ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is
transmitted by the slave, the master may issue a STOP.
I²C Read Transaction
A Read transaction consists of a START, CHIP-ADDRESS WRITE,
REGISTER-ADDRESS, START, CHIP-ADDRESS READ, DATA
BYTE(S), and STOP. Following all but the final byte the master
places an ACK on the bus (9TH clock pulse). Termination of the
Read transaction is indicated by a NACK being placed on the
bus by the master, followed by STOP.
Alternately, if the previous I²C transaction was a Read, the
internal register address buffer is still valid, allowing the
transaction to proceed without “re”-specifying the register
address. In this case the transaction consists of a START,
CHIP-ADDRESS_READ, DATA BYTE(S), and STOP. Following all but
the final byte the master places an ACK on the bus (9^TH clock
pulse). Termination of the Read transaction is indicated by a
NACK being placed on the bus by the master, followed by STOP.
The I²C bus protocol was developed by Philips (now NXP). For
a complete description of the I²C protocol, please review the
NXP I²C design specification at:
http://www.i2c-bus.org/references/
Timing Diagrams
Page 12
Document Feedback
ams Datasheet
[v1-11] 2016-Sep-20