AM186EM Datasheet, PDF (70/98 Pages) List of Unclassifed Manufacturers – MICROCONTROLLER BLOCK DIAGRAM

PRELIMINARY
SWITCHING CHARACTERISTICS over Commercial operating range
PSRAM Read Cycle (33 MHz and 40 MHz)
Parameter
No. Symbol
Description
General Timing Requirements
Preliminary
33 MHz
40 MHz
Min
Max
Min
Max Unit
1
t_DVCL Data in Setup
2
t_CLDX Data in Hold^(b)
General Timing Responses
8
5
ns
3
2
ns
5
t_CLAV AD Address Valid Delay and BHE
0
15
0
12 ns
7
t_CLDV Data Valid Delay
0
15
0
12 ns
8
t_CHDX Status Hold Time
0
0
ns
9
t_CHLH ALE Active Delay
15
12 ns
10
t_LHLL ALE Width
t_CLCL – 10 =
20
t_CLCL – 5 =
20
ns
11 t_CHLL ALE Inactive Delay
23 t_LHAV ALE High to Address Valid
80 t_CLCLX LCS Inactive Delay
81 t_CLCSL LCS Active Delay
84 t_LRLL LCS Precharge Pulse Width
Read Cycle Timing Responses
15
12 ns
10
7.5
ns
0
15
0
12 ns
0
15
0
12 ns
t_CLCL + t_CLCH
–3
t_CLCL + t_CLCH
– 1.25
ns
24 t_AZRL AD Address Float to RD Active
25 t_CLRL RD Active Delay
26 t_RLRH RD Pulse Width
0
0
ns
0
15
0
10 ns
2t_CLCL – 15
= 45
2t_CLCL – 10
= 40
ns
27 t_CLRH RD Inactive Delay
0
15
0
12 ns
28
t_RHLH RD Inactive to ALE High^(a)
t_CLCH – 3
t_CLCH – 1.25
ns
59 t_RHDX RD High to Data Hold on AD Bus^(b)
0
0
ns
66 t_AVRL A Address Valid to RD Low
2t_CLCL – 15
= 45
2t_CLCL – 10
= 40
ns
68 t_CHAV CLKOUTA High to A Address Valid
0
15
0
10 ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with C_L = 50 pF. For switching tests, V_IL = 0.45 V and V_IH = 2.4 V, except at X1 where V_IH = V_CC – 0.5 V.
a Equal loading on referenced pins.
b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
70
Am186/188EM and Am186/188EMLV Microcontrollers