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AM186EM Datasheet, PDF (67/98 Pages) List of Unclassifed Manufacturers – MICROCONTROLLER BLOCK DIAGRAM
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PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range
Write Cycle (33 MHz and 40 MHz)
Parameter
No. Symbol
Description
General Timing Responses
Preliminary
33 MHz
40 MHz
Min
Max
Min
Max Unit
3
tCHSV Status Active Delay
0
15
4
tCLSH Status Inactive Delay
0
15
5
tCLAV AD Address Valid Delay and BHE
0
15
6
tCLAX Address Hold
0
25
7
tCLDV Data Valid Delay
0
15
8
tCHDX Status Hold Time
0
9
tCHLH ALE Active Delay
15
10
tLHLL ALE Width
tCLCL – 10 =
20
0
0
0
0
0
0
tCLCL – 5
= 20
12 ns
12 ns
12 ns
20 ns
12 ns
ns
12 ns
ns
11 tCHLL ALE Inactive Delay
12
tAVLL AD Address Valid to ALE Low(a)
13
tLLAX
AD Address Hold from ALE
Inactive(a)
15
12 ns
tCLCH
tCLCH
ns
tCHCL
tCHCL
ns
14 tAVCH AD Address Valid to Clock High
16 tCLCSV MCS/PCS Active Delay
17
tCXCSX
MCS/PCS Hold from Command
Inactive(a)
0
0
ns
0
15
0
12 ns
tCLCH
tCLCH
ns
18 tCHCSX MCS/PCS Inactive Delay
19
tDXDL DEN Inactive to DT/R Low(a)
20 tCVCTV Control Active Delay 1(b)
22 tCHCTV Control Active Delay 2
23 tLHAV ALE High to Address Valid
Write Cycle Timing Responses
0
15
0
12 ns
0
0
ns
0
15
0
12 ns
0
15
0
12 ns
10
7.5
ns
30 tCLDOX Data Hold Time
31 tCVCTX Control Inactive Delay(b)
32 tWLWH WR Pulse Width
33 tWHLH WR Inactive to ALE High(a)
34 tWHDX Data Hold after WR(a)
35 tWHDEX WR Inactive to DEN Inactive(a)
65 tAVWL A Address Valid to WR Low
0
0
ns
0
15
0
12 ns
2tCLCL – 10
= 50
2tCLCL – 10
= 40
ns
tCLCH – 2
tCLCH – 2
ns
tCLCL – 10 =
20
tCLCL – 10 =
15
ns
tCLCH – 5
tCLCH
ns
tCLCL +tCHCL
–3
tCLCL +tCHCL
– 1.25
ns
67 tCHCSV CLKOUTA High to LCS/UCS Valid
0
15
0
10 ns
68
tCHAV
CLKOUTA High to A Address
Valid
0
15
0
10 ns
87
tAVBL A Address Valid to WHB, WLB Low tCHCL–3
15 tCHCL–1.25 12 ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V.
a Equal loading on referenced pins.
b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
Am186/188EM and Am186/188EMLV Microcontrollers
67
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