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AM186EM Datasheet, PDF (64/98 Pages) List of Unclassifed Manufacturers – MICROCONTROLLER BLOCK DIAGRAM
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range
Read Cycle (33 MHz and 40 MHz)
Parameter
No. Symbol
Description
General Timing Requirements
1
tDVCL Data in Setup
2
tCLDX Data in Hold(c)
General Timing Responses
3
tCHSV Status Active Delay
4
tCLSH Status Inactive Delay
5
tCLAV AD Address Valid Delay and BHE
6
tCLAX Address Hold
7
tCLDV Data Valid Delay
8
tCHDX Status Hold Time
9
tCHLH ALE Active Delay
33 MHz
Min
8
3
0
0
0
0
0
0
10
tLHLL ALE Width
tCLCL – 10 = 20
11 tCHLL ALE Inactive Delay
12
tAVLL AD Address Valid to ALE Low(a)
13
tLLAX
AD Address Hold from ALE
Inactive(a)
tCLCH –2
tCHCL– 2
14 tAVCH AD Address Valid to Clock High
15 tCLAZ AD Address Float Delay
16 tCLCSV MCS/PCS Active Delay
17
tCXCSX
MCS/PCS Hold from Command
Inactive(a)
0
tCLAX = 0
0
tCLCH – 2
18 tCHCSX MCS/PCS Inactive Delay
0
19
tDXDL DEN Inactive to DT/R Low(a)
0
20 tCVCTV Control Active Delay 1(b)
0
21 tCVDEX DEN Inactive Delay
0
22 tCHCTV Control Active Delay 2(b)
0
23 tLHAV ALE High to Address Valid
10
Read Cycle Timing Responses
24 tAZRL AD Address Float to RD Active
0
25 tCLRL RD Active Delay
0
26 tRLRH RD Pulse Width
2tCLCL – 15 = 45
27 tCLRH RD Inactive Delay
28
tRHLH RD Inactive to ALE High(a)
0
tCLCH – 3
29
tRHAV
RD Inactive to AD Address
Active(a)
tCLCL – 10 = 20
59 tRHDX RD High to Data Hold on AD Bus(c)
0
66
tAVRL A Address Valid to RD Low(a)
2tCLCL – 15 = 45
67 tCHCSV CLKOUTA High to LCS/UCS Valid
0
68 tCHAV CLKOUTA High to A Address Valid
0
Preliminary
40 MHz
Max
Min
5
2
15
0
15
0
15
0
25
0
15
0
0
15
tCLCL – 5
= 20
15
tCLCH –2
tCHCL –2
0
15
tCLAX = 0
15
0
tCLCH – 2
15
0
0
15
0
15
0
15
0
7.5
0
15
0
2tCLCL – 10 = 40
15
0
tCLCH – 2
tCLCL – 5
= 20
0
2tCLCL – 10 = 40
15
0
15
0
Max
12
12
12
20
12
12
12
12
12
12
12
12
12
10
12
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V.
a Equal loading on referenced pins.
b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
64
Am186/188EM and Am186/188EMLV Microcontrollers