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EP2C5F256C7N Datasheet, PDF (97/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet | |||
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DC Characteristics and Timing Specifications
Table 5â7. DC Characteristics of User I/O Pins Using Single-Ended Standards Notes (1), (2) (Part 2 of 2)
I/O Standard
1.5-V HSTL class I
1.5V HSTL class II
Test Conditions
IOL (mA)
8
16
IOH (mA)
â8
â16
Voltage Thresholds
Maximum VOL (V)
0.4
0.4
Minimum VOH (V)
VC C I O â 0.4
VC C I O â 0.4
Notes to Table 5â7:
(1) The values in this table are based on the conditions listed in Tables 5â2 and 5â6.
(2) This specification is supported across all the programmable drive settings available as shown in the Cyclone II
Architecture chapter of the Cyclone II Device Handbook.
Differential I/O Standards
The RSDS and mini-LVDS I/O standards are only supported on output
pins. The LVDS I/O standard is supported on both receiver input pins
and transmitter output pins.
1 For more information on how these differential I/O standards
are implemented, refer to the High-Speed Differential Interfaces in
Cyclone II Devices chapter of the Cyclone II Device Handbook.
Figure 5â1 shows the receiver input waveforms for all differential I/O
standards (LVDS, LVPECL, differential 1.5-V HSTL class I and II,
differential 1.8-V HSTL class I and II, differential SSTL-2 class I and II, and
differential SSTL-18 class I and II).
Altera Corporation
February 2008
5â7
Cyclone II Device Handbook, Volume 1
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