|
EP2C5F256C7N Datasheet, PDF (108/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet | |||
|
◁ |
Timing Specifications
Table 5â15. Cyclone II Performance (Part 4 of 4)
Resources Used
Performance (MHz)
Applications
Larger 8-bit, 1024 pt, Quad Output,
Designs 4 Parallel FFT Engines, Buffered
Burst, 3 Mults/5 Adders FFT
function
8-bit, 1024 pt, Quad Output,
4 Parallel FFT Engines, Buffered
Burst, 4 Mults/2 Adders FFT
function
LEs
M4K
Memory
Blocks
DSP
Blocks
â6
Speed
Grade
8053 60
36 200.0
â7
Speed
Grade
(6)
â7
Speed
Grade
(7)
â8
Speed
Grade
195.0 149.23 163.02
7453 60
48 200.0 195.0 151.28 163.02
Notes to Table 5â15 :
(1) This application uses registered inputs and outputs.
(2) This application uses registered multiplier input and output stages within the DSP block.
(3) This application uses the same clock source for both A and B ports.
(4) This application uses independent clock sources for A and B ports.
(5) This application uses PLL clock outputs that are globally routed to connect and drive M4K clock ports. Use of
non-PLL clock sources or local routing to drive M4K clock ports may result in lower performance numbers than
shown here. Refer to the Quartus II timing report for actual performance numbers.
(6) These numbers are for commercial devices.
(7) These numbers are for automotive devices.
Internal Timing
Refer to Tables 5â16 through 5â19 for the internal timing parameters.
Table 5â16. LE_FF Internal Timing Microparameters (Part 1 of 2)
Parameter
TSU
TH
TCO
TCLR
â6 Speed Grade (1)
Min
Max
â36
â
â
â
266
â
â
â
141
250
â
â
191
â
â
â
â7 Speed Grade (2)
Min
Max
â40
â
â38
â
306
â
286
â
135
277
141
â
244
â
217
â
â8 Speed Grade (3)
Unit
Min
Max
â40
â
ps
â40
â
ps
306
â
ps
306
â
ps
135
304
ps
141
â
ps
244
â
ps
244
â
ps
5â18
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
|
▷ |