EP2C5F256C7N Datasheet, PDF (31/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

Cyclone II Architecture
Figure 2–12. EP2C15 & Larger PLL, CLK[], DPCLK[] & Clock Control Block Locations
DPCLK[11..10]
DPCLK[9..8]
CDPCLK7
CLK[11..8]
CDPCLK6
2
2
4
CDPCLK0
DPCLK0
CLK[3..0]
DPCLK1
CDPCLK1
PLL 3
4
PLL 2
3
CDPCLK5
(2)
(2)
GCLK[15..0]
Clock Control
Block (1)
4
3
DPCLK7
16
16
16
4
CLK[7..4]
4
16
4
3
(2)
Clock Control
Block (1)
GCLK[15..0]
(2)
3
DPCLK6
CDPCLK4
PLL 1
PLL 4
4
4
2
2
CDPCLK2
CLK[15..12]
DPCLK[3..2]
DPCLK[5..4]
CDPCLK3
Notes to Figure 2–12:
(1) There are four clock control blocks on each side.
(2) Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time. The other CDPCLK pins
can be used as general-purpose I/O pins.
Altera Corporation
February 2007
2–19
Cyclone II Device Handbook, Volume 1