EP2C5F256C7N Datasheet, PDF (159/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

DC Characteristics and Timing Specifications
Figure 5–10. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
clk
INPUT
VCC
DFF
PRN
DQ
GND
CLRN
1
0
V_{CC DFF}
PRN
DQ
CLRN
output
Altera Corporation
February 2008
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
Tables 5–55 through 5–58 give the maximum DCD in absolution
derivation for different I/O standards on Cyclone II devices. Examples
are also provided that show how to calculate DCD as a percentage.
Table 5–55. Maximum DCD for Single Data Outputs (SDR) on Row I/O
Pins Notes (1), (2) (Part 1 of 2)
Row I/O Output Standard
LVCMOS
LVTTL
2.5-V
1.8-V
1.5-V
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
HSTL-15 Class I
HSTL-18 Class I
C6
C7
C8
Unit
165
230
230
ps
195
255
255
ps
120
120
135
ps
115
115
175
ps
130
130
135
ps
60
90
90
ps
65
75
75
ps
90
165
165
ps
145
145
205
ps
85
155
155
ps
5–69
Cyclone II Device Handbook, Volume 1