EP2C5F256C7N Datasheet, PDF (157/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

DC Characteristics and Timing Specifications
Table 5–54. PLL Specifications Note (1) (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
f_{V C O} (3)
t_{A R E S E T}
PLL internal VCO operating range
300
Minimum pulse width on areset signal.
10
—
1,000
MHz
—
—
ns
Notes to Table 5–54:
(1) These numbers are preliminary and pending silicon characterization.
(2) The t_JITTER specification for the PLL[4..1]_OUT pins are dependent on the I/O pins in its VCCIO bank, how many
of them are switching outputs, how much they toggle, and whether or not they use programmable current strength.
(3) If the VCO post-scale counter = 2, a 300- to 500-MHz internal VCO frequency is available.
(4) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency
is different for each I/O standard.
(5) Cyclone II PLLs can track a spread-spectrum input clock that has an input jitter within ±200 ps.
(6) For extended temperature devices, the maximum lock time is 500 us.
Duty Cycle
Distortion
Duty cycle distortion (DCD) describes how much the falling edge of a
clock is off from its ideal position. The ideal position is when both the
clock high time (CLKH) and the clock low time (CLKL) equal half of the
clock period (T), as shown in Figure 5–8. DCD is the deviation of the
non-ideal falling edge from the ideal falling edge, such as D1 for the
falling edge A and D2 for the falling edge B (Figure 5–8). The maximum
DCD for a clock is the larger value of D1 and D2.
Figure 5–8. Duty Cycle Distortion
Ideal Falling Edge
CLKH = T/2
CLKL = T/2
D1 D2
Falling Edge A
Falling Edge B
Clock Period (T)
DCD expressed in absolution derivation, for example, D1 or D2 in
Figure 5–8, is clock-period independent. DCD can also be expressed as a
percentage, and the percentage number is clock-period dependent. DCD
as a percentage is defined as:
Altera Corporation
February 2008
5–67
Cyclone II Device Handbook, Volume 1