EP2C5F256C7N Datasheet, PDF (120/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

Timing Specifications
IOE Programmable Delay
Refer to Table 5–36 and 5–37 for IOE programmable delay.
Table 5–36. Cyclone II IOE Programmable Delay on Column Pins Notes (1), (2)
Fast Corner
Number
(3)
Parameter Paths Affected of
–6 Speed
Grade
–7 Speed
Grade
(4)
–8 Speed
Grade
Unit
Settings _{Min Max Min Max Min Max Min Max}
Offset Offset Offset Offset Offset Offset Offset Offset
Input Delay Pad -> I/O
7
from Pin to dataout to core
Internal
Cells
0 2233 0 3827 0 4232 0 4349 ps
0 2344 — —
0 4088 —
— ps
Input Delay Pad -> I/O
8
0 2656 0 4555 0 4914 0 4940 ps
from Pin to input register
Input
0 2788 — —
0 4748 —
— ps
Register
Delay from I/O output
2
Output
register -> Pad
Register to
Output Pin
0 303 0 563 0
638
0
670 ps
0 318 — —
0 617 —
— ps
Notes to Table 5–36:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version
of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting “0” as available in the Quartus II
software.
(3) The value in the first row for each parameter represents the fast corner timing parameter for industrial and
automotive devices. The second row represents the fast corner timing parameter for commercial devices.
(4) The value in the first row is for automotive devices. The second row is for commercial devices.
Table 5–37. Cyclone II IOE Programmable Delay on Row Pins Notes (1), (2) (Part 1 of 2)
Parameter
Paths
Affected
Number
of
Settings
Fast Corner (3)
Min Max
Offset Offset
–6 Speed
Grade
Min Max
Offset Offset
–7 Speed
Grade (4)
Min Max
Offset Offset
–8 Speed Grade
Unit
Min Max
Offset Offset
Input Delay Pad ->
7
from Pin to I/O
Internal dataout
Cells
to core
0
2240
0
3776
0
4174
0
4290 ps
0 2352 —
—
0 4033 —
— ps
5–30
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008