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EP2C5F256C7N Datasheet, PDF (137/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet
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DC Characteristics and Timing Specifications
= 1000 / (1000/toggle rate at default load + derating factor * load
value in pF/1000)
For example, the output toggle rate at 0 pF (default) load for SSTL-18
Class II 18mA I/O standard is 270 MHz on a –6 device column I/O pin.
The derating factor is 29 ps/pF. For a 10pF load, the toggle rate is
calculated as:
1000 / (1000/270 + 29 × 10/1000) = 250 (MHz)
Tables 5–44 through 5–46 show the I/O toggle rates for Cyclone II
devices.
Table 5–44. Maximum Input Clock Toggle Rate on Cyclone II Devices (Part 1 of 2)
Maximum Input Clock Toggle Rate on Cyclone II Devices (MHz)
I/O Standard
LVTTL
2.5V
1.8V
1.5V
LVCMOS
SSTL_2_CLASS_I
SSTL_2_CLASS_II
SSTL_18_CLASS_I
SSTL_18_CLASS_II
1.5V_HSTL_CLASS_I
1.5V_HSTL_CLASS_II
1.8V_HSTL_CLASS_I
1.8V_HSTL_CLASS_II
PCI
PCI-X
DIFFERENTIAL_SSTL_2_
CLASS_I
DIFFERENTIAL_SSTL_2_
CLASS_II
Column I/O Pins
Row I/O Pins
Dedicated Clock
Inputs
–6 –7 –8 –6 –7 –8 –6 –7 –8
Speed Speed Speed Speed Speed Speed Speed Speed Speed
Grade Grade Grade Grade Grade Grade Grade Grade Grade
450 405 360 450 405 360 420 380 340
450 405 360 450 405 360 450 405 360
450 405 360 450 405 360 450 405 360
300 270 240 300 270 240 300 270 240
450 405 360 450 405 360 420 380 340
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
—
—
— 350 315 280 350 315 280
—
—
— 350 315 280 350 315 280
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
Altera Corporation
February 2008
5–47
Cyclone II Device Handbook, Volume 1
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