EP2C5F256C7N Datasheet, PDF (52/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

I/O Structure & Features
Figure 2–22. Column I/O Block Connection to the Interconnect
28 Data &
Control Signals
from Logic Array (1)
I/O Block
Local Interconnect
Column I/O Block
28
io_datain0[3..0]
io_datain1[3..0] (2)
R4 & R24 Interconnects
Column I/O
Block Contains
up to Four IOEs
io_clk[5..0]
LAB
LAB
LAB
LAB Local
Interconnect
C4 & C24 Interconnects
Notes to Figure 2–22:
(1) The 28 data and control signals consist of four data out lines, io_dataout[3..0], four output enables,
io_coe[3..0], four input clock enables, io_cce_in[3..0], four output clock enables, io_cce_out[3..0],
four clocks, io_cclk[3..0], four asynchronous clear signals, io_caclr[3..0], and four synchronous clear
signals, io_csclr[3..0].
(2) Each of the four IOEs in the column I/O block can have two io_datain (combinational or registered) inputs.
2–40
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007