EP2C5F256C7N Datasheet, PDF (36/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

Global Clock Network & Phase-Locked Loops
Figure 2–15. LAB & I/O Clock Regions
Column I/O Clock Region
IO_CLK[5..0]
6
Cyclone Logic Array
LAB Row Clocks
labclk[5..0]
6
6
LAB Row Clocks
labclk[5..0]
6
6
LAB Row Clocks
labclk[5..0]
6
LAB Row Clocks
labclk[5..0]
6
Global Clock
Network
8 or 16
LAB Row Clocks
labclk[5..0]
6
6
LAB Row Clocks
labclk[5..0]
6
I/O Clock Regions
6
6
Row I/O Clock
Region
IO_CLK[5..0]
6
6
Column I/O Clock Region
IO_CLK[5..0]
I/O Clock Regions
f
For more information on the global clock network and the clock control
block, see the PLLs in Cyclone II Devices chapter in Volume 1 of the
Cyclone II Device Handbook.
2–24
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007