EP20K30ETC144-2N Datasheet, PDF (93/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 69. EP20K160E f_MAX Routing Delays
Symbol
-1
-2
t_F1-4
t_F5-20
t_F20+
Min
Max
Min
Max
0.25
0.26
1.00
1.18
1.95
2.19
-3
Unit
Min
Max
0.28
ns
1.35
ns
2.30
ns
Table 70. EP20K160E Minimum Pulse Width Timing Parameters
Symbol
t_CH
t_CL
t_CLRP
t_PREP
t_ESBCH
t_ESBCL
t_ESBWP
t_ESBRP
-1
Min
Max
1.34
1.34
0.18
0.18
1.34
1.34
1.15
0.93
-2
Min
Max
1.43
1.43
0.19
0.19
1.43
1.43
1.45
1.15
-3
Unit
Min
Max
1.55
ns
1.55
ns
0.21
ns
0.21
ns
1.55
ns
1.55
ns
1.73
ns
1.38
ns
Table 71. EP20K160E External Timing Parameters
Symbol
t_{I N S U}
t_{I N H}
t_{O U T C O}
t_{I N S U P L L}
t_{I N H P L L}
t_{O U T C O P L L}
-1
Min
Max
2.23
0.00
2.00
5.07
2.12
0.00
0.50
3.00
-2
Min
Max
2.34
0.00
2.00
5.59
2.07
0.00
0.50
3.35
-3
Unit
Min
Max
2.47
ns
0.00
ns
2.00
6.13
ns
-
ns
-
ns
-
-
ns
Altera Corporation
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