EP20K30ETC144-2N Datasheet, PDF (31/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Figure 18. Deep Memory Block Implemented with Multiple ESBs
Address Decoder
ESB
ESB
to System Logic
ESB
The ESB implements two forms of dual-port memory: read/write clock
mode and input/output clock mode. The ESB can also be used for
bidirectional, dual-port memory applications in which two ports read or
write simultaneously. To implement this type of dual-port memory, two
or four ESBs are used to support two simultaneous reads or writes. This
functionality is shown in Figure 19.
Figure 19. APEX 20K ESB Implementing Dual-Port RAM
Clock A
Port A
address_a[]
data_a[]
we_a
clkena_a
Port B
address_b[]
data_b[]
we_b
clkena_b
Clock B
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