EP20K30ETC144-2N Datasheet, PDF (58/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 22 shows the JTAG timing parameters and values for APEX 20K
devices.
f
Generic Testing
Table 22. APEX 20K JTAG Timing Parameters & Values
Symbol
Parameter
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
t_JPXZ
t_JSSU
t_JSH
t_JSCO
t_JSZX
t_JSXZ
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Min Max Unit
100
ns
50
ns
50
ns
20
ns
45
ns
25 ns
25 ns
25 ns
20
ns
45
ns
35 ns
35 ns
35 ns
For more information, see the following documents:
■ Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in
Altera Devices)
■ Jam Programming & Test Language Specification
Each APEX 20K device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for APEX 20K
devices are made under conditions equivalent to those shown in
Figure 32. Multiple test patterns can be used to configure devices during
all stages of the production flow.
58
Altera Corporation